OIF 112G RTLR

Canonical Summary

OIF EEI-112G-RTLR sets a 112 Gb/s PAM4 chip-to-module link from 36 to 56 GSym/s.

Lead Organization

OIF

Key Technical Metric

112 Gb/s PAM4

Maturity / Status

IA 01.0 (2025-10-01)

Governance / License

OIF Implementation Agreement

Technical Specifications

Document OIF-EEI-112G-RTLR-01.0

Revision date 1 October 2025, revision 01.0 forwarded for publication

Cover line PDF header still says Draft Implementation Agreement

Interface 112 Gb/s chip-to-module PAM4

Baud 36 to 56 GSym/s; Ethernet rate 53.125 GSym/s

Channel Up to 16 dB loss at Nyquist, including one connector

Egress reference OIF CEI-112G-VSR-PAM4, or IEEE 802.3 Annex 120G with host PCB budget limited to 11.9 dB

Error ratio Raw BER of 2.8x10^-4 or better; FEC assumed to reach a corrected BER of 10^-13

Verification: verified · Retrieved: 2026-10-19 · Primary Source Reference